View ADV7171KSUZ-REEL_5098407.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

digital pal/ntsc video encoder with 10-bit ssaf? and advanced power management adv7170/adv7171 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2009 analog devices, inc. all rights reserved. features itu-r 1 bt601/656 ycrcb to pal/ntsc video encoder high quality 10-bit video dacs ssaf (super sub-alias filter) advanced power management features cgms (copy generation management system) wss (wide screen signalling) simultaneous y, u, v, c output format ntsc m, pal m/n 2 , pal b/d/g/h/i, pal60 single 27 mhz clock required (2 oversampling) 80 db video snr 32-bit direct digital synthesizer for color subcarrier multistandard video output support composite (cvbs) components s-video (y/c), yuv, and rgb euroscart output (rgb + cvbs/luma) component yuv + chroma video input data port supports ccir-656 4:2:2 8-bit parallel input format 4:2:2 16-bit parallel input format programmable simultaneous composite and s-video or rgb (scart)/yuv video outputs programmable luma filters (low-pass [pal/ntsc]) notch, ex tended (ssaf, cif, and qcif ) programmable chroma filters (low-pass [0.65 mhz, 1.0 mhz, 1.2 mhz and 2.0 mhz], cif and qcif) programmable vbi (vertical blanking interval) programmable subcarrier frequency and phase programmable luma delay individual on/off control of each dac ccir and square pixel operation integrated subcarrier locking to external video source color signal control/ burst signal control interlaced/noninterlaced operation complete on-chip video timing generator programmable multimode master/slave operation macrovision? antitaping rev. 7.1 (adv7170 only) 3 closed captioning support teletext insertion port (pal-wst) on-board color bar generation on-board voltage reference 2-wire serial mpu interface (i 2 c?-compatible and fast i 2 c) single supply 5 v or 3.3 v operation small 44-lead mqfp/tqfp packages industrial temperature grade = ?40c to +85c 4 applications high performance dvd playback systems, portable video equipment including digital still cameras and laptop pcs, video games, pc video/multimedia and digital satellite/cable systems (set-top boxes/ird) 1 itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). 2 throughout the document n is referenced to pal- combination -n. 3 protected by u.s. patents 4,631,603;, 4,577,216, 4,819,098; and other intellectual property rights. the macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. please contact sales office for latest macrovision version available. 4 refer to table 8 for complete operating details. 10-bit dac 10 10-bit dac 10 10-bit dac 10 10 10-bit dac 10 10 10 m u l t i p l e x e r dac d (pin 27) dac c (pin 26) dac b (pin 31) dac a (pin 32) v ref r set comp voltage reference circuit adv7170/adv7171 gnd screset/rtc alsb ttxreq ttx sdata sclock clock real-time control circuit i 2 c mpu port video timing generator 4:2:2 to 4:4:4 inter- polator 8 v 8 u 8 y 8 8 8 8 8 9 8 8 9 ycrcb to yuv matrix add burst add sync power management control (sleep mode) v aa reset color data p7?p0 p15?p8 hsync blank field/vsync inter- polator inter- polator programmable luminance filter programmable chrominance filter cgms and wss insertion block teletext insertion block 10 10 10 u v 10 10 sin/cos dds block yuv to rgb matrix 00221-001 figure 1. functional block diagram protected by u.s. patents 5,343,196; 5,442,355; and other intellectual property rights.
adv7170/adv7171 rev. c | page 2 of 64 table of contents specifications ..................................................................................... 4 ? dynamic specifications ............................................................... 6 ? timing specifications .................................................................. 7 ? timing diagrams.......................................................................... 9 ? absolute maximum ratings .......................................................... 10 ? package thermal performance ................................................. 10 ? esd caution ................................................................................ 10 ? pin configuration and function descriptions ........................... 11 ? general description ....................................................................... 13 ? data path description ................................................................ 13 ? internal filter response ............................................................. 14 ? typical performance characteristics ........................................... 15 ? features ............................................................................................ 18 ? color bar generation ................................................................ 18 ? square pixel mode ...................................................................... 18 ? color signal control .................................................................. 18 ? burst signal control ................................................................... 18 ? ntsc pedestal control ............................................................. 18 ? pixel timing description .......................................................... 18 ? subcarrier reset .......................................................................... 18 ? real-time co ntrol ..................................................................... 18 ? video timing description ........................................................ 18 ? power-on reset .......................................................................... 26 ? sch phase mode ........................................................................ 26 ? mpu port description ............................................................... 26 ? register accesses ........................................................................ 27 ? register programming ................................................................... 28 ? subaddress register (sr7 to sr0) ............................................ 28 ? register select (sr5 to sr0) ...................................................... 28 ? mode register 0 mr0 (mr07 to mr00) ................................. 28 ? mr0 bit description .................................................................. 28 ? mode register 1 mr1 (mr17 to mr10) ................................. 30 ? mr1 bit description .................................................................. 30 ? mode register 2 mr2 (mr27 to mr20) ................................. 30 ? mr2 bit description .................................................................. 30 ? mode register 3 mr3 (mr37 to mr30) .................................... 32 ? mr3 bit description .................................................................... 32 ? mode register 4 mr4 (mr47 to mr40) ................................. 33 ? mr4 bit description .................................................................. 33 ? vsync _3h (mr43) .................................................................. 33 ? timing mode register 0 (tr07 to tr00) ............................... 33 ? tr0 bit description ................................................................... 34 ? timing mode register 1 (tr17 to tr10) ............................... 34 ? tr1 bit description ................................................................... 34 ? subcarrier frequency registers 0 to 3 (fsc3 to fsc0) ......... 35 ? subcarrier phase registers (fp7 to fp0) ................................. 35 ? closed captioning even field data register 1 to 0 (ced15 to ced0) .......................................................................................... 35 ? closed captioning odd field data registers 1 to 0 (ccd15 to ccd0) ..................................................................................... 35 ? ntsc pedestal/pal teletext control registers 3 to 0 (pce15 to pce0, pco15 to pco0)/(txe15 to txe0, txo15 to txo0) .......................................................................................... 36 ? teletext request control register tc07 (tc07 to tc00) .... 36 ? cgms_wss register 0 c/w0 (c/w07 to c/w00) .............. 36 ? c/w0 bit description ................................................................ 36 ? cgms_wss register 1 c/w1 (c/w17 to c/w10) .............. 37 ? c/w1 bit description ................................................................ 37 ? cgms data bits (c/w17 to c/w16) ...................................... 37 ? cgms_wss register 2 c/w1 (c/w27 to c/w20) .............. 37 ? c/w2 bit description ................................................................ 37 ? appendices ...................................................................................... 38 ? appendix 1board design and layout considerations...... 38 ?
adv7170/adv7171 rev. c | page 3 of 64 appendix 2closed captioning .............................................. 40 ? appendix 3copy generation management system (cgms) ........................................................................................ 41 ? appendix 4wide screen signaling ....................................... 42 ? appendix 5teletext insertion ................................................ 43 ? appendix 6waveforms ........................................................... 44 ? appendix 7optional output filter ....................................... 48 ? appendix 8optional dac buffering ................................... 48 ? appendix 9recommended register values ........................ 49 ? appendix 10output waveforms ........................................... 51 ? outline dimensions ........................................................................ 61 ? ordering guide ........................................................................... 62 ? revision history 3/09rev. b to rev. c changes to table 8 .......................................................................... 10 updated outline dimensions ........................................................ 61 added figure 103, renumbered figures sequentially ............... 61 changes to ordering guide ........................................................... 61 6/05rev. a to rev. b updated format .................................................................. universal changes to features section ............................................................ 1 changes to table 8 .......................................................................... 10 changes to square pixel mode section ........................................ 18 changes to figure 37 ...................................................................... 29 changes to figure 42 ...................................................................... 33 changes to subcarrier frequency registers 3 to 0 section ....... 35 changes to figure 45 ...................................................................... 35 changes to figure 82 ...................................................................... 48 changes to ordering guide ........................................................... 62 6/02starting rev. a to rev. b changes to specifications ................................................................. 3 changes to package thermal performance section...9
adv7170/adv7171 rev. c | page 4 of 64 specifications v aa = 5 v 5% 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted. table 1. parameter conditions 1 min typ max unit static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity r set = 300 0.6 lsb differential nonlinearity guaranteed monotonic 1 lsb digital inputs input high voltage, v inh 2 v input low voltage, v inl 0.8 v input current, i in v in = 0.4 v or 2.4 v 1 a input capacitance, c in 10 pf digital outputs output high voltage, v oh i source = 400 a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 a three-state output capacitance 10 pf analog outputs output current 3 r set = 150 , r l = 37.5 3 34.7 37 ma output current 4 r set = 1041 , r l = 262.5 5 ma dac-to-dac matching 1.5 % output compliance, v oc 0 +1.4 v output impedance, r out 30 k output capacitance, c out i out = 0 ma 30 pf voltage reference reference range, v ref i vrefout = 20 a 1.142 1.235 1.327 v power requirements 5 v aa 4.75 5.0 5.25 v normal power mode i dac (max) 6 r set = 150 , r l = 37.5 150 155 ma i dac (min) 6 r set = 1041 , r l = 262.5 20 ma i cct 7 75 95 ma low power mode i dac (max) 6 80 ma i dac (min) 6 20 ma i cct 7 75 95 ma sleep mode i dac 8 0.1 a i cct 9 0.001 a power supply rejection ratio comp = 0.1 f 0.01 0.5 %/% 1 the min/max specifications are guaranteed over this range. the min/max values are typical over 4.75 v to 5.25 v. 2 ambient temperature range t min to t max : ?40c to +85c. the die temperature, t j , must always be kept below 110c. 3 full drive into 37.5 doubly terminated load. 4 minimum drive current (used with buffered/scaled output load). 5 power measurements are taken with clock frequency = 27 mhz. max t j = 110c. 6 i dac is the total current (min corresponds to 5 ma output per dac; max corresponds to 37 ma output per dac) to drive all four dacs. turning off individual dacs reduces i dac correspondingly. 7 i cct (circuit current) is the continuous current required to drive the device. 8 total dac current in sleep mode. 9 total continuous current during sleep mode.
adv7170/adv7171 rev. c | page 5 of 64 v aa = 3.0 v to 3.6 v 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted. table 2. parameter conditions 1 min typ max unit static performance 3 resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity r set = 300 0.6 lsb differential nonlinearity guaranteed monotonic 1 lsb digital inputs 3 input high voltage, v inh 2 v input low voltage, v inl 0.8 v input current, i in 3 , 4 v in = 0.4 v or 2.4 v 1 a input capacitance, c in 10 pf digital outputs 3 output high voltage, v oh i source = 400 a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 a three-state output capacitance 10 pf analog outputs 3 output current 4 , 5 r set = 150 , r l = 37.5 33 34.7 37 ma output current 6 r set = 1041 , r l = 262.5 5 ma dac-to-dac matching 2.0 % output compliance, v oc 0 1.4 v output impedance, r out 30 k output capacitance, c out i out = 0 ma 30 pf power requirements 3 , 7 v aa 3.0 3.3 3.6 v normal power mode i dac (max) 8 r set = 150 , r l = 37.5 150 155 ma i dac (min) 8 r set = 1041 , r l = 262.5 20 ma i cct 9 35 ma low power mode i dac (max) 8 80 ma i dac (min) 8 20 ma i cct 9 35 ma sleep mode i dac 10 0.1 a i cct 11 0.001 a power supply rejection ratio comp = 0.1 f 0.01 0.5 %/% 1 the min/max specifications are guaranteed over this range. the min/max values are typical over 3.0 v to 3.6 v. 2 ambient temperature range t min to t max : ?40c to +85c. the die temperature, t j , must always be kept below 110c. 3 guaranteed by characterization. 4 full drive into 37.5 load. 5 dacs can output 35 ma typically at 3.3 v (r set = 150 and r l = 37.5 ); optimum performance obtained at 18 ma dac current (r set = 300 and r l = 75 ). 6 minimum drive current (used with buffered/scaled output load). 7 power measurements are taken with clock frequency = 27 mhz. max t j = 110c. 8 i dac is the total current (min corresponds to 5 ma output per dac, max corresponds to 38 ma output per dac) to drive all four dacs. turning off individual dacs reduces i dac correspondingly. 9 i cct (circuit current) is the continuous current required to drive the device. 10 total dac current in sleep mode. 11 total continuous current during sleep mode.
adv7170/adv7171 rev. c | page 6 of 64 dynamic specifications v aa = 5 v 5% 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted. table 3. parameter conditions 1 min typ max unit differential gain 3 , 4 normal power mode 0.3 0.7 % differential phase 3 , 4 normal power mode 0.4 0.7 degrees differential gain 3 , 4 lower power mode 1.0 2.0 % differential phase 3 , 4 lower power mode 1.0 2.0 degrees snr 3 , 4 (pedestal) rms 80 db rms snr 3 , 4 (pedestal) peak periodic 70 db p-p snr 3 , 4 (ramp) rms 60 db rms snr 3 , 4 (ramp) peak periodic 58 db p-p hue accuracy 3 , 4 0.7 1.2 degrees color saturation accuracy 3 , 4 0.9 1.4 % chroma nonlinear gain 3 , 4 referenced to 40 ire 0.6 % chroma nonlinear phase 3 4 0.3 0.5 degrees chroma/luma intermod 3 , 4 0.2 0.4 % chroma/luma gain inequality 3 , 4 1.0 1.4 % chroma/luma delay inequality 3 , 4 0.5 2.0 ns luminance nonlinearity 3 , 4 0.8 1.4 % chroma am noise 3 , 4 82 85 db chroma pm noise 3 , 4 79 81 db 1 the min/max specifications are guaranteed over this range. the min/max values are typical over 4.75 v to 5.25 v. 2 ambient temperature range t min to t max : ?40c to +85c. the die temperature, t j , must always be kept below 110c. 3 guaranteed by characterization. 4 these specifications are for the low-pass filter only and are guaranteed by design. v aa = 3.0 v to 3.6 v 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted. table 4. parameter conditions 1 min typ max unit differential gain 3 normal power mode 1.0 % differential phase 3 normal power mode 0.5 degrees differential gain 3 lower power mode 0.6 % differential phase 3 lower power mode 0.5 degrees snr3 (pedestal) rms 78 db rms snr3 (pedestal) peak periodic 70 db p-p snr3 (ramp) rms 60 db rms snr3 (ramp) peak periodic 58 db p-p hue accuracy 3 1.0 degrees color saturation accuracy 3 1.0 % luminance nonlinearity 3 , 4 1.4 % chroma am noise 3 , 4 80 db chroma pm noise 3 , 4 79 db chroma nonlinear gain 3 , 4 referenced to 40 ire 0.6 % chroma nonlinear phase 3 , 4 0.3 0.5 degrees chroma/luma intermod 3 , 4 0.2 0.4 % 1 the min/max specifications are guaranteed over this range. the min/max values are typical over 4.75 v to 5.25 v. 2 ambient temperature range t min to t max : ?40c to +85c. the die temperature, t j , must always be kept below 110c. 3 guaranteed by characterization. 4 these specifications are for the low-pass filter only and are guaranteed by design. for other internal filters, see table 10.
adv7170/adv7171 rev. c | page 7 of 64 timing specifications v aa = 4.75 v to 5.25 v 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted. table 5. parameter conditions min typ max unit mpu port 3 , 4 sclock frequency 0 400 khz sclock high pulse width, t 1 0.6 s sclock low pulse width, t 2 1.3 s hold time (start condition), t 3 after this period the first clock is generated relevant for repeated start condition 0.6 s setup time (start condition), t 4 0.6 s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s analog outputs 3 , 5 analog output delay 7 ns dac analog output skew 0 ns clock control and pixel port 5 , 6 f clock 27 mhz clock high time, t 9 8 ns clock low time, t 10 8 ns data setup time, t 11 3.5 ns data hold time, t 12 4 ns control setup time, t 11 4 ns control hold time, t 12 3 ns digital output access time, t 13 11 16 ns digital output hold time, t 14 4 8 ns pipeline delay, t 15 4 48 clock cycles teletext 3 , 4 , 7 digital output access time, t 16 20 ns data setup time, t 17 2 ns data hold time, t 18 6 ns reset control 3 , 4 reset low time 6 ns 1 the min/max specifications are guaranteed over this range. the min/max values are typical over 4.75 v to 5.25 v range. 2 ambient temperature range t min to t max : ?40c to +85c. the die temperature, t j , must always be kept below 110c. 3 ttl input values are 0 v to 3 v, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf. 4 guaranteed by characterization 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 pixel port consists of the following: pixel inputs: p15Cp0 pixel controls: hsync , field/ vsync , blank clock input: clock 7 teletext port consists of the following: teletext output: ttxreq teletext input: ttx
adv7170/adv7171 rev. c | page 8 of 64 v aa = 3.0 v to 3.6 v 1 , v ref = 1.235 v, r set = 150 . all specifications t min to t max 2 , unless otherwise noted. table 6. parameter conditions min typ max unit mpu port 3 , 4 sclock frequency 0 400 khz sclock high pulse width, t 1 0.6 s sclock low pulse width, t 2 1.3 s hold time (start condition), t 3 after this period the first clock is generated relevant for repeated start condition 0.6 s setup time (start condition), t 4 0.6 s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s analog outputs 3 , 5 analog output delay 7 ns dac analog output skew 0 ns clock control and pixel port 4 , 5 , 6 f clock 27 mhz clock high time, t 9 8 ns clock low time, t 10 8 ns data setup time, t 11 3.5 ns data hold time, t 12 4 ns control setup time, t 11 4 ns control hold time, t 12 3 ns digital output access time, t 13 12 ns digital output hold time, t 14 8 ns pipeline delay, t 15 48 clock cycles teletext 3 , 4 , 7 digital output access time, t 16 23 ns data setup time, t 17 2 ns data hold time, t 18 6 ns reset control 3 , 4 reset low time 6 ns 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v range. 2 ambient temperature range t min to t max : ?40c to +85c. the die temperature, t j , must always be kept below 110c. 3 ttl input values are 0 v to 3 v, with input rise/fall times 3 ns, measured between the 10% an d 90% points. timing reference p oints at 50% for inputs and outputs. analog output load 10 pf. 4 guaranteed by characterization 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition 6 pixel port consists of the following: pixel inputs: p15Cp0 pixel controls: hsync , field/ vsync , blank clock input: clock 7 teletext port consists of the following: teletext output: ttxreq teletext input: ttx
adv7170/adv7171 rev. c | page 9 of 64 timing diagrams t 3 t 1 t 6 t 2 t 7 t 5 sdata sclock t 3 t 4 t 8 00221-002 figure 2. mpu port timing diagram t 9 t 11 clock pixel input data t 10 t 12 hsync, field/vsync, blank cb y cr y cb y hsync, field/vsync, blank t 14 control i/ps control o/ps t 13 00221-003 figure 3. pixel and control data timing diagram t 16 t 17 t 18 ttxreq clock ttx 4 clock cycles 4 clock cycles 4 clock cycles 3 clock cycles 4 clock cycles 00221-004 figure 4. teletext timing diagram
adv7170/adv7171 rev. c | page 10 of 64 absolute maximum ratings table 7. parameter rating v aa to gnd 7 v voltage on any digital input pin gnd ? 0.5 v to v aa + 0.5 v storage temperature (t s ) ?65c to +150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec) 260c analog outputs to gnd 1 gnd ? 0.5 v to v aa 1 analog output short circuit to any power supply or gnd can be of an indefinite duration. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. package thermal performance the 44-mqfp package used for this device takes advantage of an adi patented thermal coastline lead frame construction. this maximizes heat transfer into the leads and reduces the package thermal resistance. for the mqfp package, the junction-to-ambient ( ja ) thermal resistance in still air on a four-layer pcb is 35.5c/w. the junction-to-case thermal resistance ( jc ) is 13.75c/w. for the tqfp package, ja in still air on a four-layer pcb is 53.2c/w. jc is 11.1c/w. junction temperature = t j = [v aa ( dac output current + i cct ) ja ] + ambient temperature. table 8. allowable operating conditions for ks and ksu package options ks, wbs ksu conditions 3 v 5 v 3 v 5 v 4 dac on double 75r 1 yes +70c max +70c max no 4 dac on low power 2 yes yes yes no 4 dac on buffering 3 yes yes yes yes 3 dac on double 75r yes yes yes no 3 dac on low power yes yes yes yes 3 dac on buffering yes yes yes yes yes yes yes yes yes yes yes yes 4 dac on buffering yes yes 1 dac on double 75r refers to a cond ition where the dacs are terminated in a double 75r load and low power mode is disabled. 2 dac on low power refers to a cond ition where the dacs are terminated in a double 75r load and low power mode is enabled. 3 dac on buffering refers to a condit ion where the dac current is reduced to 5 ma and external buffers are used to drive the video load. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adv7170/adv7171 rev. c | page 11 of 64 pin configuration and fu nction descriptions 44 clock 43 gnd 42 p4 41 p3 40 p2 39 p1 38 p0 37 ttx 36 ttxreq 35 screset/rt c 34 r set 32 dac a 31 dac b 30 v aa 27 dac d 28 v aa 29 gnd 33 v ref 26 dac c 25 comp 24 sdata 23 sclock 2 p5 3 p6 4 p7 7 p10 6 p9 5 p8 1 v aa 8 p11 9 p12 10 gnd 11 v aa 12 p13 13 p14 14 p15 15 hsync 16 field/vsync 17 blank 18 alsb 19 gnd 20 v aa 21 gnd 22 reset pin 1 adv7170/adv7171 mqfp/tqfp top view (not to scale) 00221-005 figure 5. pin configuration table 9. pin function descriptions pin no. mnemonic input/ output description 1, 11, 20, 28, 30 v aa p power supply (3 v to 5 v). 2 to 9, 12 to 14, 38 to 42 p15 to p0 i 8-bit 4:2:2 multiplexed ycrcb pixel port (p7 to p0) or 16-bit ycrcb pixel port (p15 to p0). p0 represents the lsb. 10, 19, 21, 29, 43 gnd g ground pin. 15 hsync i/o hsync (mode 1 and mode 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) sync signals. 16 field/ vsync i/o dual function field (mode 1) and vsync (mode 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) these control signals. 17 blank i/o video blanking control signal. the pixel inputs are ignored when this is logic level 0. this signal is optional. 18 alsb i ttl address input. this signal sets up the lsb of the mpu address. 22 reset i the input resets the on-chip timing genera tor and sets the adv 7170/adv7171 into default mode. this is ntsc operation, timing slave mo de 0, 8-bit operation, 2 composite and s-video out, and dac b powered on and dac d powered off. 23 sclock i mpu port serial interface clock input. 24 sdata i/o mpu port seri al data input/output. 25 comp o compensation pin. connect a 0.1 f capacitor from comp to v aa . for optimum dynamic performance in low power mode, the value of the comp capacitor can be lowered to as low as 2.2 nf. 26 dac c o red/s-video c/v analog output. 27 dac d o green/s-video y/y analog output. 31 dac b o blue/composite/u analog output. 32 dac a o pal/ntsc composite video output. fu ll-scale output is 180 ire (1286 mv) for ntsc and 1300 mv for pal. 33 v ref i/o voltage reference input for dacs or voltage reference output (1.235 v). 34 r set i a 150 resistor connected from this pin to gnd is used to control full-scale amplitudes of the video signals.
adv7170/adv7171 rev. c | page 12 of 64 pin no. mnemonic input/ output description 35 screset/rtc i this pin can be configured as an in put by setting mr22 and mr21 of mode register 2. it can be configured as a subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to field 0. alternatively, it may be configured as a real-time control (rtc) input. 36 ttxreq o teletext data request signal. defaul ts to gnd when teletext not selected. enables backward compatibility to adv7175/adv7176. 37 ttx i teletext data. defaults to v aa when teletext not selected. enables backward compatibility to adv7175/adv7176. 44 clock i ttl clock input. requires a stable 27 mhz reference clock for standard operation. alternatively, a 24.5454 mhz (ntsc) or 29.5 mhz (pal) can be used for square pixel operation.
adv7170/adv7171 rev. c | page 13 of 64 general description the adv7170/adv7171 are integrated digital video encoders that convert digital ccir-601 4:2:2 8- or 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards. the on-board ssaf (super sub-alias filter) with extended luminance frequency response and sharp stop band attenuation enables studio-quality video playback on modern tvs, giving optimal horizontal line resolution. an advanced power management circuit enables optimal control of power consumption in both normal operating modes and power-down or sleep modes. the adv7170/adv7171 support both pal and ntsc square pixel operation. the parts also incorporate wss and cgms-a data control generation. the output video frames are synchronized with the incoming data timing reference codes. optionally, the encoder accepts and can generate hsync , vsync , and field timing signals. these timing signals can be adjusted to change pulse width and position while the part is in the master mode. the encoder requires a single, two-times pixel rate (27 mhz) clock for standard operation. alternatively, the encoder requires a 24.5454 mhz clock for ntsc or 29.5 mhz clock for pal square pixel mode operation. all internal timing is generated on-chip. a separate teletext port enables the user to directly input teletext data during the vertical blanking interval. the adv7170/adv7171 modes are set up over a 2-wire, serial bidirectional port (i 2 c-compatible) with two slave addresses. functionally, the adv7170 and adv7171 are the same with the exception that the adv7170 can output the macrovision anticopy algorithm. the adv7170/adv7171 are packaged in a 44-lead mqfp package and a 44-lead tqfp package. data path description for pal b/d/g/h/i/m/n, and ntsc m and n modes, ycrcb 4:2:2 data is input via the ccir-656 compatible pixel port at a 27 mhz data rate. the pixel data is demultiplexed to form three data paths. y typically has a range of 16 to 235; cr and cb typically have a range of 128 112. however, it is possible to input data from 1 to 254 on y, cb, and cr. the adv7170/ adv7171 support pal (b, d, g, h, i, m, n) and ntsc (with and without pedestal) standards. the appropriate sync, blank , and burst levels are added to the ycrcb data. macrovision antitaping (adv7170 only), closed-captioning, and teletext levels are also added to y, and the resultant data is interpolated to a rate of 27 mhz. the interpolated data is filtered and scaled by three digital fir filters. the u and v signals are modulated by the appropriate sub- carrier sine/cosine phases and added together to make up the chrominance signal. the luma (y) signal can be delayed 1 to 3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. the luma and chroma signals are then added together to make up the composite video signal. all edges are slew rate limited. the ycrcb data is also used to generate rgb data with appropriate sync and blank levels. the rgb data is in synchronization with the composite video output. alternatively, analog yuv data can be generated instead of rgb. the four 10-bit dacs can be used to output the following: composite video + rgb video. composite video + yuv video. two composite video signals + luma and chroma (y/c) signals. alternatively, each dac can be individually powered off if not required. video output levels are illustrated in appendix 6waveforms .
adv7170/adv7171 rev. c | page 14 of 64 internal filter response the y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (ssaf) response, a cif response, and a qcif response. the uv filter supports several different frequency responses, including four low -pass responses, a cif response, and a qcif response that are shown in tabl e 10 and tabl e 11 and figure 6 to figure 18 . table 10. luminance internal filter specifications filter type filter selection mr04 mr03 mr02 pass-band ripple (db) 3 db bandwidth (mhz) stop-band cutoff (mhz) stop-band attenuation (db) low pass (ntsc) 0 0 0 0.091 4.157 7.37 ?56 low pass (pal) 0 0 1 0.15 4.74 7.96 ?64 notch (ntsc) 0 1 0 0.015 6.54 8.3 ?68 notch (pal) 0 1 1 0.095 6.24 8.0 ?66 extended (ssaf) 1 0 0 0.051 6.217 8.0 ?61 cif 1 0 1 0.018 3.0 7.06 ?61 qcif 1 1 0 monotonic 1.5 7.15 ?50 table 11. chrominance internal filter specifications filter type filter selection mr07 mr06 mr05 pass-band ripple (db) 3 db bandwidth (mhz) stop-band cutoff (mhz) stop-band attenuation (db) 1.3 mhz low pass 0 0 0 0.084 1.395 3.01 ?45 .65 mhz low pass 0 0 1 monotonic 0.65 3.64 ?58.5 1.0 mhz low pass 0 1 0 monotonic 1.0 3.73 ?49 2.0 mhz low pass 0 1 1 0.0645 2.2 5.0 ?40 reserved 1 0 0 cif 1 0 1 0.084 0.7 3.01 ?45 qcif 1 1 0 monotonic 0.5 4.08 ?50
adv7170/adv7171 rev. c | page 15 of 64 typical performance characteristics 0 ?70 0 00221-006 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 6. ntsc low-pass luma filter 0 ?70 0 00221-007 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 7. pal low-pass luma filter 0 ?70 0 00221-008 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 8. ntsc notch luma filter 0 ?70 0 00221-009 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 9. pal no tch luma filter 0 ?70 0 00221-010 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 10. extended mode (ssaf) luma filter 0 ?70 0 00221-011 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 11. cif luma filter
adv7170/adv7171 rev. c | page 16 of 64 0 ?70 0 00221-012 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 12. qcif luma filter 0 ?70 0 00221-013 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 13. 1.3 mhz low-pass chroma filter 0 ?70 0 00221-014 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 14. 0.65 mhz low-pass chroma filter 0 ?70 0 00221-015 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 15. 1.0 mhz low-pass chroma filter 0 ?70 0 00221-016 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 16. 2.0 mhz low-pass chroma filter 0 ?70 0 00221-017 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 17. cif chroma filter
adv7170/adv7171 rev. c | page 17 of 64 0 ?70 0 00221-018 frequency (mhz) magnitude (db) ?10 ?20 ?30 ?40 ?50 ?60 2 4 6 8 10 12 figure 18. qcif chroma filter
adv7170/adv7171 rev. c | page 18 of 64 features color bar generation the adv7170/adv7171 can be configured to generate 100/7.5/75/7.5 color bars for ntsc or 100/0/75/0 color bars for pal. these are enabled by setting mr17 of mode register 1 to logic level 1. square pixel mode the adv7170/adv7171 can be used to operate in square pixel mode. for ntsc operation, an input clock of 24.5454 mhz is required. alternatively, for pal operation, an input clock of 29.5 mhz is required. the internal timing logic adjusts accordingly for square pixel mode operation. when the adv7171 is configured for pal square pixel mode, it supports 768 active pixels per line. ntsc square pixel mode supports 640 active pixels per line. color signal control the color information can be switched on and off the video output using bit mr24 of mode register 2. burst signal control the burst information can be switched on and off the video output using bit mr25 of mode register 2. ntsc pedestal control the pedestal on both odd and even fields can be controlled on a line-by-line basis using the ntsc pedestal control registers. this allows the pedestals to be controlled during the vertical blanking interval. pixel timing description the adv7170/adv7171 operate in either 8-bit or 16-bit ycrcb mode. 8-bit ycrcb mode this default mode accepts multiplexed ycrcb inputs through the p7 to p0 pixel inputs. the inputs follow the sequence cb0, y0 cr0, y1 cb1, y2, and so on. the y, cb, and cr data are input on a rising clock edge. 16-bit ycrcb mode this mode accepts y inputs through the p7 to p0 pixel inputs and multiplexed crcb inputs through the p15 to p8 pixel inputs. the data is loaded on every second rising edge of clock. the inputs follow the sequence cb0, y0 cr0, y1 cb1, y2, and so on. subcarrier reset together with the screset/rtc pin and bit mr22 and bit mr21 of mode register 2, the adv7170/adv7171 can be used in subcarrier reset mode. the subcarrier resets to field 0 at the start of the following field when a low-to-high transition occurs on this input pin. real-time control together with the screset/rtc pin and bit mr22 and bit mr21 of mode register 2, the adv7170/adv7171 can be used to lock to an external video source. the real-time control mode allows the adv7170/adv7171 to automatically alter the subcarrier frequency to compensate for line length variation. when the part is connected to a device that outputs a digital data stream in the rtc format (such as a adv7185 video decoder, shown in figure 19 ), the part automatically changes to the compensated subcarrier frequency on a line-by-line basis. this digital data stream is 67 bits wide, and the subcarrier is contained in bit 0 to bit 21. each bit is 2 clock cycles long. 00hex should be written into all four subcarrier frequency registers when using this mode. video timing description the adv7170/adv7171 are intended to interface to off-the- shelf mpeg1 and mpeg2 decoders. consequently, the adv7170/adv7171 accept 4:2:2 ycrcb pixel data via a ccir-656 pixel port, and they have several video timing modes of operation that allow them to be configured as either system master video timing generators or as slaves to the system video timing generator. the adv7170/adv7171 generate all of the required horizontal and vertical timing periods and levels for the analog video outputs. the adv7170/adv7171 calculate the width and placement of analog sync pulses, blanking levels, and color burst envelopes. color bursts are disabled on appropriate lines, and serration and equalization pulses are inserted where required. in addition, the adv7170/adv7171 support a pal or ntsc square pixel operation in slave mode. the part requires an input pixel clock of 24.5454 mhz for ntsc and an input pixel clock of 29.5 mhz for pal. the internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. the adv7170/adv7171 have four distinct master and four distinct slave timing configurations. timing control is established with the bidirectional sync , blank , and field/ vsync pins. timing mode register 1 can also be used to vary the timing pulse widths where they occur in relation to each other.
adv7170/adv7171 rev. c | page 19 of 64 hsync field/vsync clock green/luma/y red/chroma/v blue/composite/u composite adv7170/adv7171 p7?p0 screset/rtc h/ltransition count start low 128 rtc time slot: 01 14 67 68 not used in adv7170/adv7171 19 valid sample invalid sample f sc pll increment 1 8/llc 5 bits reserved sequence bit 2 reset bit 3 reserved 4 bits reserved 21 0 13 14 bits reserved 0 video decoder (for example, adv7185) composite video (for example, vcr or cable) notes: 1 f sc pll increment is 22 bits long, value loaded into adv7170/adv7171 fsc dds register is f sc pll increments bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the adv7170/adv7171. 2 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 3 reset bit reset adv7170/adv7171 dds 00221-019 figure 19. rtc timing and connections vertical blanking data insertion it is possible to allow encoding of incoming ycbcr data on those lines of vbi that do not bear line sync or pre-/post- equalization pulses (see figure 21 to figure 32 ). this mode of operation is called partial blanking and is selected by setting mr32 to 1. it allows the insertion of any vbi data (opened vbi) into the encoded output waveform. this data is present in the digitized incoming ycbcr data stream (for example, wss data, cgms, vps, and so on). alternatively, the entire vbi may be blanked (no vbi data inserted) on these lines by setting mr32 to 0. mode 0 (ccir-656): slave option (timing register 0 tr0 = x x x x x 0 0 0) the adv7170/adv7171 are controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchroni- zation pattern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. mode 0 is shown in figure 20 . the hsync , field/ vsync , and blank (if not used) pins should be tied high during this mode. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y 00221-020 figure 20. timing mode 0 (slave mode)
adv7170/adv7171 rev. c | page 20 of 64 mode 0 (ccir-656): master option (timing register 0 tr0 = x x x x x 0 0 1) the adv7170/adv7171 generate h, v, and f signals required for the sa v (start active video) and eav (end active video) time code s in the ccir656 standard. the h bit is output on the hsync pin, the v bit is output on the blank pin, and the f bit is output on the field/ vsync pin. mode 0 is illustrated in (ntsc) and (pal). the h, v, and f transitions relative to the video waveform are illustrated in . figure 21 figure 22 figure 23 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f 00221-021 figure 21. timing mode 0 (ntsc master mode)
adv7170/adv7171 rev. c | page 21 of 64 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 00221-022 figure 22. timing mode 0 (pal master mode) a nalo g video h f v 00221-023 figure 23. timing mode 0 data transitions (master mode)
adv7170/adv7171 rev. c | page 22 of 64 mode 1: slave option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 0) in this mode the adv7170/adv7171 accept horizontal sync and od d/even field signals. a transi tion of the field input when hsync is low indicates a new frame, that is, vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7170/adv7171 automatically blank all normally blan k lines as per ccir-624. mode 1 is illustrated in (ntsc) and (pal). figure 24 figure 25 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display hsync blank field 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display odd field even field blank field vertical blank vertical blank hsync 00221-024 figure 24. timing mode 1 (ntsc) 622 623 624 625 1 2 3 4 5 67 21 22 23 display odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display odd field even field hsync blank field display 320 vertical blank vertical blank 00221-025 figure 25. timing mode 1 (pal)
adv7170/adv7171 rev. c | page 23 of 64 mode 1: master option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 1) in this mode the adv7170/adv7171 can generate horizontal sync and odd/even field signals. a transi tion of the field input when hsync is low indicates a new frame, that is, vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7170/adv7171 automatically blank all normally blank lines as per ccir-624. pixel data is latched on the rising clock edge fo llowing the timing signal transitions. mode 1 is shown in (ntsc) and (pal). illustrates the figure 24 figure 25 figure 26 hsync , blank , and field for an odd or even field transition relative to the pixel data. field pixel data pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y hsync blank 00221-026 figure 26. timing mode 1 odd/even field transitions master/slave mode 2: slave option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 0) in this mode the adv7170/adv7171 accept horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the adv7170/adv7171 automatically blank all normally blank lines as per ccir-624. mode 2 is illustrated in (ntsc) and (pal). figure 27 figure 28 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display odd field even field hsync blank vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display hsync blank vsync vertical blank 00221-027 vertical blank figure 27. timing mode 2 (ntsc)
adv7170/adv7171 rev. c | page 24 of 64 622 623 624 625 1 2 3 4 5 67 21 22 23 display odd field even field hsync blank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display odd field even field hsync blank display 320 vsync vertical blank vertical blank 00221-028 figure 28. timing mode 2 (pal) mode 2: master option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 1) in this mode the adv7170/adv7171 can generate horizontal and vertical snc signals. a coincident low transition of both hsnc and vsnc inputs indicates the start of an odd field. a vsnc low transition when hsnc is high indicates the start of an even field. the blank signal is optional. hen the blank input is disabled the adv7170/adv7171 automaticall blank all normall blank lines as per ccir-624. mode 2 is shown in (ntsc) and (pal). shows the figure 27 figure 28 figure 29 hsnc blank and vsnc for an even-to-odd field transition relative to the pixel data. shows the figure 30 hsnc blank and vsnc for an odd-to-even field transition relative to the pixel data. pal = 12 clock/2 ntsc = 16 clock/2 hsync vsync pixel data pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y blank 00221-029 figure 29. timing mode 2 even-to- odd field transiti on master/slave pal = 864 clock/2 ntsc = 858 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 hsync vsync pixel data pal = 12 clock/2 ntsc = 16 clock/2 cb y cr y cb blank 00221-030 figure 30. timing mode 2 odd-to-ev en field transiti on master/slave
adv7170/adv7171 rev. c | page 25 of 64 mode 3: master/slave option hsync , blank , field (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode the adv7170/adv7171 accept or generate horizontal sync and odd/even field signals. a transition of the field input when hsync is high indicates a new frame, that is, vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7170/adv7171 automatically blank all normally blank lines as per ccir-624. mode 3 is shown in (ntsc) and (pal). figure 31 figure 32 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field blank field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 display display vertical blank hsync odd field blank field hsync even field 00221-031 figure 31. timing mode 3 (ntsc) 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank odd field even field blank field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank odd field even field 313 hsync field hsync blank 00221-032 figure 32. timing mode 3 (pal)
adv7170/adv7171 rev. c | page 26 of 64 power-on reset after power-up, it is necessary to execute a reset operation. a reset occurs on the falling edge of a high-to-low transition on the reset pin. this initializes the pixel port so that the pixel inputs, p7 to p0, are selected. after reset, the adv7170/ adv7171 is automatically set up to operate in ntsc mode. subcarrier frequency code 21f07c16hex is loaded into the subcarrier frequency registers. all other registers, with the exception of mode register 0, are set to 00h. all bits in mode register 0 are set to logic level 0, except bit mr44. bit mr44 of mode register 4 is set to logic level 1. this enables the 7.5 ire pedestal. sch phase mode the sch phase is configured in default mode to reset every four (ntsc) or eight (pal) fields to avoid an accumulation of sch phase error over time. in an ideal system, zero sch phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. this effect is reduced by the use of a 32-bit dds, which generates this sch. resetting the sch phase every four or eight fields avoids the accumulation of sch phase error and results in very minor sch phase jumps at the start of the four or eight field sequence. resetting the sch phase should not be done if the video source does not have stable timing or the adv7170/adv7171 are configured in rtc mode (mr21 = 1 and mr22 = 1). under these conditions (unstable video), the subcarrier phase reset should be enabled (mr22 = 0 and mr21 = 1) but no reset applied. in this configuration the sch phase is never reset, which means the output video tracks the unstable input video. the subcarrier phase reset, when applied, resets the sch phase to field 0 at the start of the next field (for example, subcarrier phase reset applied in field 5 [pal] on the start of the next field sch phase resets to field 0). mpu port description the adv7170/adv7171 support a 2-wire, serial (i 2 c- compatible) microprocessor bus driving multiple peripherals. two inputs, serial data (sdata), and serial clock (sclock), carry information between any devices connected to the bus. each slave device is recognized by a unique address. the adv7170/adv7171 each have four possible slave addresses for both read and write operations. these are unique addresses for each device and are shown in figure 33 and figure 34 . the lsb sets either a read or write operation. logic level 1 corresponds to a read operation, while logic level 0 corre- sponds to a write operation. a 1 is set by setting the alsb pin of the adv7170/adv7171 to logic level 0 or logic level 1. 1 x 10101a1 address control set up by alsb read/write control 0 write 1 read 00221-033 figure 33. adv7170 slave address 0 x 10101a1 address control set up by alsb read/write control 0 write 1 read 00221-034 figure 34. adv7171 slave address to control the various devices on the bus, the following protocol must be followed: first, the master initiates a data transfer by establishing a start condition, defined by a high-to- low transition on sdata while sclock remains high. this indicates that an address/data stream follows. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ rw bit). the bits transfer from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sdata and sclock lines waiting for the start condition and the correct transmitted address. the r/ rw bit determines the direction of the data. a logic level 0 on the lsb of the first byte means that the master writes information to the peripheral. a logic level 1 on the lsb of the first byte means the master reads information from the peripheral.
adv7170/adv7171 rev. c | page 27 of 64 the adv7170/adv7171 act as standard slave devices on the bus. the data on the sdata pin is eight bits long, supporting the 7-bit addresses plus the r/ rw bit. the adv7170 has 48 subaddresses, and the adv7171 has 26 subaddresses to enable access to the internal registers. it therefore interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto-increment allows data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. there is one exception. the subcarrier frequency registers should be updated in sequence, starting with subcarrier frequency register 0. the auto-increment function should then be used to increment and access subcarrier frequency register 1, subcarrier frequency register 2, and subcarrier frequency register 3. the subcarrier frequency registers should not be accessed independently. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sclock high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adv7170/adv7171 do not issue an acknowledge, and they return to the idle condition. if in auto-increment mode the user exceeds the highest subaddress, the following action is taken: in read mode, the highest subaddress register contents continue to be output until the master device issues a no- acknowledge. this indicates the end of a read. a no- acknowledge condition is where the sdata line is not pulled low on the ninth pulse. in write mode, the data for the invalid byte is not loaded into any subaddress register, a no-acknowledge is issued by the adv7170/adv7171, and the part returns to the idle condition. figure 35 illustrates an example of data transfer for a read sequence and the start and stop conditions. figure 36 shows bus write and read sequences. sdata sclock start addr r/w ack subaddress ack data ack stop 1?7 8 9 s 1?7 1?7 p 00221-035 8 9 8 9 figure 35. bus data transfer register accesses the mpu can write to or read from all of the adv7170/ adv7171 registers except the subaddress register, which is a write-only register. the subaddress register determines which register the next read or write operation accesses. all commu- nications with the part through the bus start with an access to the subaddress register. a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed.
adv7170/adv7171 rev. c | page 28 of 64 register programming mode register 0 mr0 (mr07 to mr00) this section describes each register, including subaddress register, mode registers, subcarrier frequency registers, subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers, and ntsc pedestal control registers, in terms of its configuration. (address [sr4 to sr0] = 00h) figure 38 shows the various operations under the control of mode register 0. this register can be read from as well as written to. subaddress register (sr7 to sr0) mr0 bit description the communications register is an 8-bit, write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. output video standard se lection (mr01 to mr00) these bits are used to set up the encode mode. the adv7170/ adv7171 can be set up to output ntsc, pal b/d/g/h/i, and pal m/n standard video. luminance filter control (mr02 to mr04) figure 37 shows the various operations under the control of the subaddress register. zero should always be written to sr7 to sr6. these bits specify which luma filter is to be selected. the filter selection is made independent of whether pal or ntsc is selected. register select (sr5 to sr0) these bits are set up to point to the required starting address. chrominance filter control (mr05 to mr07) these bits select the chrominance filter. a low-pass filter can be selected with a choice of cutoff frequencies, 0.65 mhz, 1.0 mhz, 1.3 mhz, or 2 mhz, along with a choice of cif or qcif filters. write sequence read sequence s slave addr a(s) subaddr a(s) data data a(s) p s slave addr a(s) subaddr a(s) s slave addr a(s) data data a(m) a(m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master lsb = 0 lsb = 1 00221-036 a(s) figure 36. write and read sequences
adv7170/adv7171 rev. c | page 29 of 64 adv7171 subaddress register sr5 sr4 sr3 sr2 sr1 sr0 0 0 0 0 0 0 mode register 0 0 0 0 0 0 1 mode register 1 0 0 0 0 1 0 mode register 2 0 0 0 0 1 1 mode register 3 0 0 0 1 0 0 mode register 4 0 0 0 1 0 1 reserved 0 0 0 1 1 0 reserved 0 0 0 1 1 1 timing mode register 0 0 0 1 0 0 0 timing mode register 1 0 0 1 0 0 1 subcarrier frequency register 0 0 0 1 0 1 0 subcarrier frequency register 1 0 0 1 0 1 1 subcarrier frequency register 2 0 0 1 1 0 0 subcarrier frequency register 3 0 0 1 1 0 1 subcarrier phase register 0 0 1 1 1 0 closed captioning extended data byte 0 0 0 1 1 1 1 closed captioning extended data byte 1 0 1 0 0 0 0 closed captioning data byte 0 0 1 0 0 0 1 closed captioning data byte 1 010010 ntsc pedestal control reg 0/ pal ttx control reg 0 010011 ntsc pedestal control reg 1/ pal ttx control reg 1 010100 ntsc pedestal control reg 2/ pal ttx control reg 2 010101 ntsc pedestal control reg 3/ pal ttx control reg 3 0 1 0 1 1 0 cgms_wss_0 0 1 0 1 1 1 cgms_wss_1 0 1 1 0 0 0 cgms_wss_2 0 1 1 0 0 1 teletext request control register adv7170 subaddress register sr5 sr4 sr3 sr2 sr1 sr0 power-up/ reset value (hex) power-up/ reset value (hex) 000000 00 00 58 58 00 00 00 00 10 10 00 00 00 00 00 00 00 00 16* 16* 7c 7c f0 21 00 00 00 00 00 00 00 00 00 00 00 00 00 f0 21 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 mode register 0 0 0 0 0 0 1 mode register 1 0 0 0 0 1 0 mode register 2 0 0 0 0 1 1 mode register 3 0 0 0 1 0 0 mode register 4 0 0 0 1 0 1 reserved 0 0 0 1 1 0 reserved 0 0 0 1 1 1 timing mode register 0 0 0 1 0 0 0 timing mode register 1 0 0 1 0 0 1 subcarrier frequency register 0 0 0 1 0 1 0 subcarrier frequency register 1 0 0 1 0 1 1 subcarrier frequency register 2 0 0 1 1 0 0 subcarrier frequency register 3 0 0 1 1 0 1 subcarrier phase register 0 0 1 1 1 0 closed captioning extended data byte 0 0 0 1 1 1 1 closed captioning extended data byte 1 0 1 0 0 0 0 closed captioning data byte 0 0 1 0 0 0 1 closed captioning data byte 1 010010 ntsc pedestal control reg 0/ pal ttx control reg 0 010011 ntsc pedestal control reg 1/ pal ttx control reg 1 010100 ntsc pedestal control reg 2/ pal ttx control reg 2 010101 ntsc pedestal control reg 3/ pal ttx control reg 3 0 1 0 1 1 0 cgms_wss_0 0 1 0 1 1 1 cgms_wss_1 0 1 1 0 0 0 cgms_wss_2 0 1 1 0 0 1 teletext request control register 0 1 1 0 1 0 reserved 0 1 1 0 1 1 reserved 0 1 1 1 0 0 reserved 0 1 1 1 0 1 reserved 0 1 1 1 1 0 macrovision registers 0 1 1 1 1 1 macrovision registers 1 0 0 0 0 0 macrovision registers 1 0 0 0 0 1 macrovision registers 1 0 0 0 1 0 macrovision registers 1 0 0 0 1 1 macrovision registers 1 0 0 1 0 0 macrovision registers 1 0 0 1 0 1 macrovision registers 1 0 0 1 1 0 macrovision registers 1 0 0 1 1 1 macrovision registers 1 0 1 0 0 0 macrovision registers 1 0 1 0 0 1 macrovision registers 1 0 1 0 1 0 macrovision registers 1 0 1 0 1 1 macrovision registers 1 0 1 1 0 0 macrovision registers 1 0 1 1 0 1 macrovision registers 1 0 1 1 1 0 macrovision registers 1 0 1 1 1 1 macrovision registers sr4 sr3 sr2 sr1 sr0 sr7 sr6 sr5 zero should be written to these bits sr7?sr5 (000) 00221-037 *subcarrier frequency register 0 = 16 is incorrect on power-up for ntsc. this register should be programmed to 1f for accurate fsc. figure 37. subaddress register map
adv7170/adv7171 rev. c | page 30 of 64 mr01 mr00 mr07 mr02 mr03 mr05 mr06 mr04 mr07 mr06 mr05 000 001 010 011 100 101 110 111 1.3mhz low pass filter 0.65mhz low pass filter 1.0mhz low pass filter 2.0mhz low pass filter reserved cif q cif reserved chroma filter select mr04 mr03 mr02 000 001 010 001 100 101 110 111 low pass filter (ntsc) low pass filter (pal) notch filter (ntsc) notch filter (pal) extended mode cif q cif reserved luma filter select mr01 mr00 00 01 10 11 ntsc pal (b, d, g, h, i) pal (m) reserved output video standard selection 00221-038 figure 38. mode register 0 color bar control (mr17) mode register 1 mr1 (mr17 to mr10) this bit can be used to generate and output an internal color bar test pattern. the color bar configuration is 100/7.5/75/7.5 for ntsc and 100/0/75/0 for pal. it is important to note that when color bars are enabled, the adv7170/adv7171 are configured in a master timing mode. (address (sr4 to sr0) = 01h) figure 39 shows the various operations under the control of mode register 1 this register can be read from as well as written to mr1 bit description mode register 2 mr2 (mr27 to mr20) interlace control (mr10) (address [sr4 to sr0] = 02h) this bit is used to set up the output to interlaced or noninter- laced mode this mode is only relevant when the part is in composite video mode mode register 2 is an 8-bit-wide register figure 40 shows the various operations under the control of mode register 2 this register can be read from as well as written to closed captioning field selection (mr12 to mr11) these bits control the fields on which closed captioning data is displayed closed captioning information can be displayed on an odd field, even field, or both odd and even fields mr2 bit description square pixel control (mr20) this bit is used to set up square pixel mode this is available in slave mode only for ntsc, a 245454 mh clock must be supplied for pal, a 295 mh clock must be supplied dac control (mr16 to mr13) these bits can be used to power down the dacs this can be used to reduce the power consumption of the adv7170/ adv7171 if any of the dacs are not required in the application
adv7170/adv7171 rev. c | page 31 of 64 mr11 mr10 mr17 mr12 mr13 mr15 mr16 mr14 closed captioning field selection 0 0 no data out 0 1 odd field only 1 0 even field only 1 1 data out (both fields) mr12 mr11 dac a control 0 normal 1 power-down mr16 dac d control mr14 dac c control mr13 mr15 interlace control 0 interlaced 1 noninterlaced mr10 color bar control 0 disable 1 enable mr17 0 normal 1 power-down 0 normal 1 power-down 0 normal 1 power-down dac b control 00221-039 figure 39. mode register 1 mr21 mr27 mr22 mr23 mr26 mr25 mr24 mr20 chrominance control 0 enable color 1 disable color mr24 genlock control x 0 disable genlock 0 1 enable subcarrier reset pin 1 1 enable rtc pin mr22 mr21 low power mode 0 disable 1 enable mr26 square pixel control 0 disable 1 enable mr20 burst control 0 enable burst 1 disable burst mr25 mr27 active video line duration 0 720 pixels 1 710 pixels/702 pixels mr23 reserved 00221-040 figure 40. mode register 2 mr31 mr30 mr37 mr32 mr34 mr33 mr35 mr36 mr30 mr31 reserved vbi_open 0 disable 1 enable mr32 dac output 0 composite 1 green/luma/y mr33 dac a blue/comp/u blue/comp/u dac b red/chroma/v red/chroma/v dac c green/luma/y composite dac d chroma output select 0 disable 1 enable mr34 teletext enable 0 disable 1 enable mr35 ttxrq bit mode control 0 normal 1 bit request mr36 input default color 0 disable 1 enable mr37 00221-041 figure 41. mode register 3 genlock control (mr22 to mr21) these bits control the genlock feature of the adv7170/ adv7171. setting mr21 to a logic level 1 configures the screset/rtc pin as an input. setting mr22 to logic level 0 configures the screset/rtc pin as a subcarrier reset input. therefore, the subcarrier resets to field 0 following a low-to- high transition on the screset/rtc pin. setting mr22 to logic level 1 configures the screset/rtc pin as a real-time control input. active video line duration (mr23) this bit switches between two active video line durations. a 0 selects ccir rec601 (720 pixels pal/ntsc), and a 1 selects itu-r.bt470 standard for active video duration (710 pixels ntsc; 702 pixels pal). chrominance control (mr24) this bit enables the color information to be switched on and off the video output. burst control (mr25) this bit enables the burst information to be switched on and off the video output. low power mode (mr26) this bit enables the lower power mode of the adv7170/ adv7171, reducing the dac current by 45%.
adv7170/adv7171 rev. c | page 32 of 64 reserved (mr27) a logic level 0 must be written to this bit. mode register 3 mr3 (mr37 to mr30) (address [sr4 to sr0] = 03h) mode register 3 is an 8-bit-wide register. figure 41 shows the various operations under the control of mode register 3. mr3 bit description revision code (mr30 to mr31) these bits are read-only and indicate the revision of the device. vbi open (mr32) this bit determines whether or not data in the vertical blanking interval (vbi) is output to the analog outputs or blanked. vbi data insertion is not available in slave mode 0. also, when both blank input control and vbi-open are enabled, blank input control has priority; that is, vbi data insertion does not work. dac output (mr33) this bit is used to switch the dac outputs from scart to a euroscart configuration. a complete table of all dac output configurations is shown in table 12 . chroma output select (mr34) with this active high bit it is possible to output yuv data with a composite output on the fourth dac or a chroma output on the fourth dac (0 = cvbs; 1 = chroma). teletext enable (mr35) this bit must be set to 1 to enable teletext data insertion on the ttx pin. ttxreq bit mode control (mr36) this bit enables switching of the teletext request signal from a continuous high signal (mr36 = 0) to a bit wise request signal (mr36 = 1). input default color (mr37) this bit determines the default output color from the dacs for zero input pixel data (or disconnected). a logic level 0 means that the color corresponding to 00000000 is displayed. a logic level 1 forces the output color to black for 00000000 pixel input video data. table 12. dac output configuration matrix mr34 mr40 mr41 mr33 dac a dac b dac c dac d simultaneous output 0 0 0 0 cvbs cvbs c y 2 composite and y/c 0 0 0 1 y cvbs c cvbs 2 composite and y/c 0 0 1 0 cvbs cvbs c y 2 composite and y/c 0 0 1 1 y cvbs c cvbs 2 composite and y/c 0 1 0 0 cvbs b r g rgb and composite 0 1 0 1 g b r cvbs rgb and composite 0 1 1 0 cvbs u v y yuv and composite 0 1 1 1 y u v cvbs yuv and composite 1 0 0 0 c cvbs c y 1 composite, y and 2c 1 0 0 1 y cvbs c c 1 composite, y and 2c 1 0 1 0 c cvbs c y 1 composite, y and 2c 1 0 1 1 y cvbs c c 1 composite, y and 2c 1 1 0 0 c b r g rgb and c 1 1 0 1 g b r c rgb and c 1 1 1 0 c u v y yuv and c 1 1 1 1 y u v c yuv and c cvbs: composite video baseband signal y: luminance component signal (for yuv or y/c mode) c: chrominance signal (for y/c mode) u: chrominance component signal (for yuv mode) v: chrominance component signal (for yuv mode) r: red component vi deo (for rgb mode) g: green component video (for rgb mode) b: blue component video (for rgb mode) each dac can be powered on or off individually with the following control bits (0 = on; 1 = off): mr13-dac c mr14-dac d mr15-dac b mr16-dac a
adv7170/adv7171 rev. c | page 33 of 64 mr41 mr40 mr47 mr42 mr44 mr43 mr45 mr46 output select 0 yc output 1 rgb/yuv output mr40 rgb sync 0 disable 1 enable mr42 pedestal control 0 pedestal off 1 pedestal on mr44 sleep mode control 0 disable 1 enable mr46 active video filter control 0 disable 1 enable mr45 mr47 (0) zero should be written to this bit vsync_3h 0 disable 1 enable mr43 rgb/yuv control 0 rgb output 1 yuv output mr41 00221-042 figure 42. mode register 4 mode register 4 mr4 (mr47 to mr40) (address (sr4 to sr0) = 04h) mode register 4 is an 8-bit-wide register. figure 42 shows the various operations under the control of mode register 4. mr4 bit description output select (mr40) this bit specifies if the part is in composite video mode or rgb/yuv mode. note that in rgb/yuv mode the composite signal is still available. rgb/yuv control (mr41) this bit enables the output from the rgb dacs to be set to yuv output video standard. rgb sync (mr42) this bit is used to set up the rgb outputs with the sync information encoded on all rgb outputs. vsync _3h (mr43) when this bit is enabled (1) in slave mode, it is possible to drive the vsync active low input for 2.5 lines in pal mode and 3 lines in ntsc mode. when this bit is enabled in master mode, the adv7170/adv7171 output an active low vsync signal for 3 lines in ntsc mode and 2.5 lines in pal mode. pedestal control (mr44) this bit specifies whether a pedestal is to be generated on the ntsc composite video signal. this bit is invalid if the adv7170/adv7171 are configured in pal mode. active video filter control (mr45) this bit controls the filter mode applied outside the active video portion of the line. this filter ensures that the sync rise and fall times are always on spec regardless of which luma filter is selected. this mode is enabled by a logic level 1. sleep mode control (mr46) when this bit is set to 1, sleep mode is enabled. with this mode enabled, power consumption of the adv7170/adv7171 is reduced to typically 200 na. the i 2 c registers can be written to and read from when the adv7170/adv7171 are in sleep mode. if mr46 is set to a 0 when the device is in sleep mode, the adv7170/adv7171 come out of sleep mode and resume normal operation. also, if the reset signal is applied during sleep mode, the adv7170/adv7171 come out of sleep mode and resume normal operation. reserved (mr47) a logic level 0 should be written to this bit. timing mode register 0 (tr07 to tr00) (address [sr4 to sr0] = 07h) figure 43 shows the various operations under the control of timing register 0. this register can be read from as well as written to.
adv7170/adv7171 rev. c | page 34 of 64 tr01 tr00 tr07 tr02 tr03 tr05 tr06 tr04 timing register reset tr07 blank input control 0 enable 1 disable tr03 pixel port control 0 8 bit 1 16 bit tr06 master/slave control 0 slave timing 1 master timing tr00 luma delay 0 0 0ns delay 0 1 74ns delay 1 0 148ns delay 1 1 222ns delay tr05 tr04 timing mode selection 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 tr02 tr01 00221-043 figure 43. timing register 0 tr0 bit description master/slave control (tr00) this bit controls whether the adv7170/adv7171 is in master or slave mode. timing mode selection (tr02 to tr01) these bits control the timing mode of the adv7170/ adv7171. these modes are described in more detail in the timing and control section. blank control (tr03) this bit controls whether the blank input is used when the part is in slave mode. luma delay (tr05 to tr04) these bits control the addition of a luminance delay. each bit represents a delay of 74 ns. pixel port control (tr06) this bit is used to set the pixel port to accept 8-bit or 16-bit data. if an 8-bit input is selected, the data will be set up on pin p7 to pin p0. timing register reset (tr07) toggling tr07 from low to high and low again resets the internal timing counters. this bit should be toggled after power-up, reset or changing to a new timing mode. timing mode register 1 (tr17 to tr10) (address (sr4 to sr0) = 08h) timing register 1 is an 8-bit-wide register. figure 44 shows the various operations under the control of timing register 1. this register can be read from as well written to. this register can be used to adjust the width and position of the master mode timing signals. tr1 bit description hsync width (tr11 to tr10) these bits adjust the hsync pulse width. hsync to field/ vsync delay (tr13 to tr12) these bits adjust the position of the hsync output relative to the field/ vsync output. hsync to field rising edge delay (tr15 to tr14) when the adv7170/adv7171 are in timing mode 1, these bits adjust the position of the hsync output relative to the field output rising edge. vsync width (tr15 to tr14) when the adv7170/adv7171 are configured in timing mode 2, these bits adjust the vsync pulse width. hsync to pixel data adju st (tr17 to tr16) this enables the hsync to be adjusted with respect to the pixel data. this allows the cr and cb components to be swapped. this adjustment is available in both master timing mode and slave timing mode.
adv7170/adv7171 rev. c | page 35 of 64 tr11 tr10 tr17 tr12 tr13 tr15 tr16 tr14 hsync to pixel data adjust tr17 tr16 000 t pclk 011 t pclk 102 t pclk 113 t pclk hsync to field/vsync delay tr13 tr12 00 0 t pclk 01 4 t pclk 10 8 t pclk 11 16 t pclk t b hsync width 001 t pclk 014 t pclk 1016 t pclk 1 1 128 t pclk tr11 tr10 t a hsync to field rising edge delay (mode 1 only) x0t b x1t b + 32 s tr15 tr14 t c vsync width (mode 2 only) tr15 tr14 001 t pclk 014 t pclk 1016 t pclk 1 1 128 t pclk line 313 line 314 line 1 t b timing mode 1 (master/pal) field/vsync t c t a hsync 00221-044 figure 44. timing register 1 subcarrier frequency registers 0 to 3 (fsc3 to fsc0) (address [sr4 to sr00] = 09h to 0ch) these 8-bit-wide registers are used to set up the subcarrier frequency the value of these registers is calculated by using the following equation, rounded to the nearest integer: 32 2 27. . linevideooneincycles clockmhzofno linevideooflineoneinvalues frequency subcarrier ofno for example, in ntsc mode, fhcfd aluevfrequency subcarrier 10721 569408542 2 1716 5.227 32 = == subcarrier frequency reg 3 fsc30 fsc29 fsc27 fsc25 fsc28 fsc24 fsc31 fsc26 s ubcarrie r frequency reg 2 fsc22 fsc21 fsc19 fsc17 fsc20 fsc16 fsc23 fsc18 s ubcarrie r frequency reg 1 fsc14 fsc13 fsc11 fsc9 fsc12 fsc8 fsc15 fsc10 s ubcarrie r frequency reg 0 fsc6 fsc5 fsc3 fsc1 fsc4 fsc0 fsc7 fsc2 00221-045 figure 45. subcarrier frequency register subcarrier phase registers (fp7 to fp0) (address [sr4 to sr0] = 0dh) this 8-bit-wide register is used to set up the subcarrier phase each bit represents 141 for normal operation this register is set to 00hex closed captioning even field data register 1 to 0 (ced15 to ced0) (address [sr4Csr0] = 0e to 0fh) these 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields figure 46 shows how the high and low bytes are set up in the registers byte 1 byte 0 ced6 ced5 ced3 ced1 ced4 ced2 ced0 ced7 ced14 ced13 ced11 ced9 ced12 ced10 ced8 ced15 00221-046 figure 46. closed captioning extended data register closed captioning odd field data registers 1 to 0 (ccd15 to ccd0) (subaddress [sr4 to sr0] = 10h to 11h) these 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields figure 47 shows how the high and low bytes are set up in the registers byte 1 byte 0 ccd6 ccd5 ccd3 ccd1 ccd4 ccd2 ccd0 ccd7 ccd14 ccd13 ccd11 ccd9 ccd12 ccd10 ccd8 ccd15 00221-047 figure 47. closed captioning data register
adv7170/adv7171 rev. c | page 36 of 64 ntsc pedestal/pal teletext control registers 3 to 0 (pce15 to pce0, pco15 to pco0)/(txe15 to txe0, txo15 to txo0) (subaddress [sr4Csr0] = 12h to 15h) these 8-bit-wide registers are used to enable the ntsc pedestal/pal teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. figure 48 and figure 49 show the four control registers. a logic level 1 in any of the bits of these registers has the effect of turning the pedestal off on the equivalent line when used in ntsc. a logic level 1 in any of the bits of these registers has the effect of turning on teletext on the equivalent line when used in pal. field 1/3 pco6 pco5 pco3 pco1 pco4 pco2 pco0 pco7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pco14 pco13 pco11 pco9 pco12 pco10 pco8 pco15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 1/3 field 2/4 pce6 pce5 pce3 pce1 pce4 pce2 pce0 pce7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pce14 pce13 pce11 pce9 pce12 pce10 pce8 pce15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 2/4 00221-048 figure 48. pedestal control registers field 1/3 field 1/3 field 2/4 field 2/4 txo6 txo5 txo3 txo1 txo4 txo2 txo0 txo7 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 txo14 txo13 txo11 txo9 txo12 txo10 txo8 txo15 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 txe6 txe5 txe3 txe1 txe4 txe2 txe0 txe7 txe14 txe13 txe11 txe9 txe12 txe10 txe8 txe15 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 00221-049 figure 49. teletext control registers teletext request control register tc07 (tc07 to tc00) (address [sr4 to sr0] = 19h) teletext control register is an 8-bit-wide register. see figure 50 . ttxreq rising edge control (tc07 to tc04) these bits control the position of the rising edge of ttxreq. it can be programmed from zero clock cycles to a maximum of 15 clock cycles. see figure 59 . ttxreq falling edge control (tc03 to tc00) these bits control the position of the falling edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. this controls the active window for teletext data. increasing this value reduces the amount of teletext bits below the default of 360. if bit tc03 to bit tc00 are 00hex when bits tc07 to tc04 are changed, the falling edge of ttxreq tracks that of the rising edge (that is, the time between the falling and rising edge remains constant). see figure 59 . cgms_wss register 0 c/w0 (c/w07 to c/w00) (address [sr4 to sr0] = 16h) cgms_wss register 0 is an 8-bit-wide register. figure 51 shows the operations under the control of this register. c/w0 bit description cgms data bits (c/w03 to c/w00) these four data bits are the final four bits of the cgms data output stream. note it is cgms data only in these bit positions; that is, wss data does not share this location. cgms crc check control (c/w04) when this bit is enabled (1), the last six bits of the cgms data (that is, the crc check sequence) are calculated internally by the adv7170/adv7171. if this bi t is disabled (0), the crc values in the register are output to the cgms data stream. cgms odd field control (c/w05) when this bit is set (1), cgms is enabled for odd fields. note this is valid only in ntsc mode. cgms even field control (c/w06) when this bit is set (1), cgms is enabled for even fields. note this is valid only in ntsc mode. wss control (c/w07) when this bit is set (1), wide screen signaling is enabled. note this is valid only in pal mode.
adv7170/adv7171 rev. c | page 37 of 64 tc01 tc00 tc07 tc02 tc04 tc03 tc05 tc06 ttxreq rising edge control tc07 tc06 tc05 tc04 0 0 0 0 0 pclk 0 0 0 1 1 pclk " " " " " pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk ttxreq falling edge control tc03 tc02 tc01 tc00 0 0 0 0 0 pclk 0 0 0 1 1 pclk " " " " " pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk 00221-050 figure 50. teletext control register c/w07 c/w06 c/w05 c/w04 c/w03 c/w02 c/w01 c/w00 c/w07 wide screen signal control 0 disable 1 enable 0 disable 1 enable c/w05 cgms odd field control c/w06 cgms even field control 0 disable 1 enable c/w04 cgms crc check control 0 disable 1 enable c/w03 ? c/w00 cgms data bits 00221-051 figure 51. cgms_wss register 0 cgms_wss register 1 c/w1 (c/w17 to c/w10) (address [sr4 to sr0] = 17h) cgms_wss register 1 is an 8-bit-wide register. figure 52 shows the operations under the control of this register. c/w1 bit description cgms/wss data bits (c/w15 to c/w10) these bit locations are shared by cgms data and wss data. in ntsc mode, these bits are cgms data. in pal mode, these bits are wss data. cgms data bits (c/w17 to c/w16) these bits are cgms data bits only. cgms_wss register 2 c/w1 (c/w27 to c/w20) (address [sr4 to sr0] = 18h) cgms_wss register 2 is an 8-bit-wide register. figure 53 shows the operations under the control of this register. c/w2 bit description cgms/wss data bits (c/w27 to c/w20) these bit locations are shared by cgms data and wss data. in ntsc mode, these bits are cgms data. in pal mode, these bits are wss data. c/w17 c/w16 c/w15 c/w14 c/w13 c/w12 c/w11 c/w10 c/w15 ? c/w10 cgms/wss data bits c/w17 ? c/w16 cgms data bits 00221-052 figure 52. cgms_wss register 1 c/w27 c/w26 c/w25 c/w24 c/w23 c/w22 c/w21 c/w20 c/w27 ? c/w20 cgms/wss data bits 00221-053 figure 53. cgms_ wss register 2
adv7170/adv7171 rev. c | page 38 of 64 appendices appendix 1board design and layout considerations the adv7170/adv7171 are highly integrated circuits containing both precision analog and high speed digital circuitry. they have been designed to minimize interference effects of the high speed digital circuitry on the integrity of the analog circuitry. it is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. figure 54 shows the analog interface between the device and monitor. the layout should be optimized for lowest noise on the adv7170/adv7171 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should be minimized to minimize inductive ringing. ground planes the ground plane should encompass all adv7170/adv7171 ground pins, voltage reference circuitry, power supply bypass circuitry for the adv7170/adv7171, the analog output traces, and all the digital signal traces leading up to the adv7170/ adv7171. the ground plane is the boards common ground plane. power planes the adv7170, the adv7171, and any associated analog circuitry should each have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within three inches of the adv7170/adv7171. the metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7170/adv7171 power pins and voltage reference circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode. supply decoupling for optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is obtained with 0.1 f ceramic capacitor decoupling. each group of v aa pins on the adv7170/ adv7171 must have at least one 0.1 f decoupling capacitor to gnd. these capacitors should be placed as close as possible to the device. it is important to note that while the adv7170/adv7171 contain circuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three- terminal voltage regulator for supplying power to the analog power plane. digital signal interconnect the digital inputs to the adv7170/adv7171 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the adv7170/adv7171 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ) and not to the analog power plane. analog signal interconnect the adv7170/adv7171 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the outputs should each have a 75 load resistor connected to gnd. these resistors should be placed as close as possible to the adv7170/adv7171 to minimize reflections. the adv7170/adv7171 should have no inputs left floating. any inputs that are not required should be tied to ground.
adv7170/adv7171 rev. c | page 39 of 64 75 75 75 75 150 5k 5k 5v (v cc ) 5v (v cc ) 100 100 mpu bus 10, 19, 21, 29, 43 27 dac d 26 dac c 31 dac b 32 dac a 23 sclock 24 sdata 34 r set 1, 11, 20, 28, 30 v aa adv7170/ adv7171 25 comp 33 v ref 35 screset/rtc 15 hsync 16 field/vsync 17 blank 22 reset 37 ttx 36 ttxreq 44 clock p15?p0 38?42, 2?9, 12?14 18 alsb gnd 5v (v aa ) 5v (v aa ) 0.1 f 0.1 f unused inputs should be grounded 10k 5v (v aa ) 27mhz clock (same clock as used by mpeg2 decoder) teletext pull-up and pull-down resistors should only be used if these pins are not connected 100nf 5v (v aa ) 4k 5v (v cc ) 100k 100k reset ttx ttxreq power supply decoupling for each power supply group 0.1 f 0.01 f 10 f 5v (v aa ) l1 (ferrite bead) 33 f 5v v cc gnd s-video 00221-054 figure 54. recommended analog circuit layout the circuit in figure 55 can be used to generate a 13.5 mhz waveform using the 27 mhz clock and the hsync pulse. this waveform is guaranteed to produce the 13.5 mhz clock in synchronization with the 27 mhz clock. this 13.5 mhz clock can be used if a 13.5 mh z clock is required by the mpeg decoder. this guarantees that the cr and cb pixel information is input to the adv7170/adv7171 in the correct sequence. d q ck d q ck cloc k hsync 13.5mhz 00221-055 figure 55. circuit to generate 13.5 mhz
adv7170/adv7171 rev. c | page 40 of 64 appendix 2closed captioning the adv7170/adv7171 support closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of the odd fields line 21 and the even fields line 284. closed captioning consists of a 7-cycle sinusoidal burst that is frequency- and phase-locked to the caption data. after the clock run-in signal, the blanking level is held for two data bits and is followed by a logic level 1 start bit. 16 bits of data follow the start bit. these consist of two 8-bit bytes, seven data bits and one odd parity bit. the data for these bytes is stored in closed captioning data register 0 and closed captioning data register 1. the adv7170/adv7171 also support the extended closed captioning operation, which is active during even fields and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data register 0 and closed captioning extended data register 1. all clock run-in signals and timing to support closed captioning on line 21 and line 284 are automatically generated by the adv7170/adv7171. all pixel inputs are ignored during line 21 and line 284. fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for line 21 and line 284. the adv7170/adv7171 use a single buffering method. this means that the closed captioning buffer is only one byte deep; therefore, there is no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. the data must be loaded at least one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, which in turn loads the new data (two bytes) in every field. if no new data is required for transmission, you must insert zeros in both the data registers; this is called nulling. it is also important to load control codes, all of which are double bytes, on line 21, or a tv does not recognize them. if you have a message like hello world, which has an odd number of characters, it is important to pad it out to an even number to get end-of-caption, 2-byte control code to land in the same field. s t a r t p a r i t y p a r i t y d0?d6 d0?d6 10.003 s 33.764 s 50 ire 40 ire reference color burst (9 cycles) frequency = f sc = 3.579545mhz amplitude = 40 ire 7 cycles of 0.5035mhz (clock run-in) 10.5 0.25 s two 7-bit + parity ascii characters (data) 27.382 s byte 0 byte 1 00221-056 12.91 s figure 56. closed captioning waveform (ntsc)
adv7170/adv7171 rev. c | page 41 of 64 appendix 3copy generation management system (cgms) the adv7170/adv7171 support copy generation management systems (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd fields and line 283 of even fields. bit c/w05 and bit c/w06 control whether or not cgms data is output on odd and even fields. cgms data can only be transmitted when the adv7170/adv7171 are configured in ntsc mode. the cgms data is 20 bits long; the function of each of these bits is shown below. the cgms data is preceded by a reference puls e of the same amplitude and duration as a cgms bit (see figure 57 ). the bits are output from the configuration registers in the following order: c/w00 = c16, c/w01 = c17, c/w02 = c18, c/w03 = c19, c/w10 = c8, c/w11 = c9, c/ w12 = c10, c/w13 = c11, c/w14 = c12, c/w15 = c13, c/w16 = c14, c/w17 = c15, c/w20 = c0, c/w21 = c1, c/w22 = c2, c/w23 = c3, c/w24 = c4, c/w25 = c5, c/w26 = c6, c/w27 = c7. if the bit c/w04 is set to a logic level 1, the last six bits, c19 to c14, which comprise the 6-bit crc check sequence, are cal culated automatically on the adv7170/adv7171 based on the lower 14 bits (c0 to c13) of the data in the data registers and output with t he remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if c/w04 is set to a logic level 0, all 20 bits (c0 to c19) are directly output from th e cgms registers (no crc is calculated; it must be calculated by the user). function of cgms bits word 0 C 6 bits word 1 C 4 bits word 2 C 6 bits crc C 6 bits crc polynomial = x 6 + x + 1 (preset to 111111) word 0 1 0 b1 aspect ratio 16:94:3 b2 display format letterbox normal b3 undefined word 0 b4, b5, b6 identification information about video and other signals (for example, audio) word 1 b7, b8, b9, b10 identification signal incidental to word 0 word 2 b11, b12, b13, b14 identification signal and information incidental to word 0 crc sequence 49.1 s 0.5 s 11.2 s 2.235 s 20ns ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 +100 ire +70 ire 0 ire ?40 ire 00221-057 figure 57. cgms waveform diagram
adv7170/adv7171 rev. c | page 42 of 64 appendix 4wide screen signaling the adv7170/adv7171 support wide screen signaling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the adv7170/adv7171 are configured in pal mode. the wss data is 14 bits long; the functio n of each of these bits is as shown below. the wss data is preceded by a run-in sequence and a start code (see figure 58 ). the bits are output from the configuration registers in the following order: c/w20 = w0, c/w21 = w1, c/w22 = w2, c/w23 = w3, c/w24 = w4, c/w25 = w5, c/w26 = w6, c/w27 = w7, c/w10 = w8, c/w11 = w9, c/w12 = w10, c/w13 = w11, c/w14 = w12, c/w15 = w13. if bit c/w07 is set to a logic level 1, it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42 .5 s from the falling edge of hsync ) is available for the insertion of video. function of cgms bits bit 0 to bit 2 aspect ratio/format/position bit 3 is odd parity check of bit 0 to bit 2 b0 b1 b2 b3 aspect ratio format position 0 0 0 1 4:3 full format nonapplicable 1 0 0 0 14:9 letterbox center 0 1 0 0 14:9 letterbox top 1 1 0 1 16:9 letterbox center 0 0 1 0 16:9 letterbox top 1 0 1 1 >16:9 letterbox center 0 1 1 1 14:9 full format center 1 1 1 0 16:9 nonapplicable nonapplicable b4 0 camera mode 1 film mode b5 0 standard coding 1 motion adaptive color plus b6 0 no helper 1 modulated helper b7 reserved b9 b10 0 0 no open subtitles 1 0 subtitles in active image area 0 1 subtitles out of active image area 1 1 reserved b11 0 no surround sound information 1 surround sound mode b12 reserved b13 reserved 11.0 s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 500mv run-in sequence start code active video 38.4 s 42.5 s 00221-058 figure 58. wss waveform diagram
adv7170/adv7171 rev. c | page 43 of 64 appendix 5teletext insertion the t pd is the time needed by the adv7170/adv7171 to interpolate input data on ttx and insert it onto the cvbs or y outputs, such that it appears t synttxout = 10.2 s after the leading edge of the horizontal signal. time ttx del is the pipeline delay time by the source that is gated by the ttxreq signal in order to deliver ttx data. with the programmability offered with the ttxreq signal on the rising/falling edges, the ttx data is always inserted at the correct position of 10.2 s after the leading edge of horizontal sync pulse, thus enabling a source interface with variable pipeline delays. the width of the ttxreq signal must always be maintained to allow the insertion of 360 (to comply with the teletext standard of pal-wst) teletext bits at a text data rate of 6.9375 mbits/sec; this is achieved by setting tc03 to tc00 to 0. the insertion window is not open if the teletext enable bit (mr35) is set to 0. teletext protocol the relationship between the ttx bit clock (6.9375 mhz) and the system clock (27 mhz) for 50 hz is as follows: (27 mhz/4) = 6.75 mhz (6.9375 10 6 /6.75 10 6 ) = 1.027777 thus, 37 ttx bits correspond to 144 clocks (27 mhz), and each bit has a width of nearly four clock cycles. the adv7170/ adv7171 use an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal that can be output on the cvbs and y outputs. at the ttx input, the bit duration scheme repeats after every 37 ttx bits or 144 clock cycles. the protocol requires that ttx bit 10, bit 19, bit 28, and bit 37 are carried by three clock cycles; all other bits are carried by four clock cycles. after 37 ttx bits, the next bits with three clock cycles are bit 47, bit 56, bit 65, and bit 74. this scheme holds for all following cycles of 37 ttx bits, until all 360 ttx bits are completed. all teletext lines are implemented in the same way. individual control of teletext lines is controlled by teletext setup registers. address and data run-in clock teletext vbi line 45 bytes (360 bits) ? pal 00221-059 figure 59. tele text vbi line programmable pulse edges t pd t pd cvbs/y hsync ttxreq t tx data t synttxout 10.2 s ttx del ttx st t synttxout = 10.2 s t pd = pipeline delay through adv7170/adv7171 ttx del = ttxreq to ttx (programmable range = 4 bits [0?15 clock cycles]) 00221-060 figure 60. teletext functionality diagram
adv7170/adv7171 rev. c | page 44 of 64 appendix 6waveforms ntsc waveforms (with pedestal) +130.8 ire +100 ire +7.5 ire 0 ire ?40 ire peak composite ref white black level sync level blank level 714.2mv 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv 00221-061 figure 61. ntsc composite video levels +100 ire +7.5 ire 0 ire ?40 ire ref white black level sync level blank level 714.2mv 1048.4mv 387.6mv 334.2mv 48.3mv 00221-062 figure 62. ntsc luma video levels 650mv 335.2mv 963.8mv 0mv peak chroma blank/black level 286mv p-p 629.7mv p-p peak chroma 00221-063 figure 63. ntsc chroma video levels +100 ire +7.5 ire 0 ire ?40 ire ref white black level sync level blank level 720.8mv 1052.2mv 387.5mv 331.4mv 45.9mv 00221-064 figure 64. ntsc rgb video levels
adv7170/adv7171 rev. c | page 45 of 64 ntsc waveforms (without pedestal) +130.8 ire +100 ire 0 ire ? 40 ire peak composite ref white sync level blank/black level 714.2mv 1289.8mv 1052.2mv 338mv 52.1mv 00221-065 figure 65. ntsc composite video levels +100 ire 0 ire ?40 ire ref white sync level blank/black level 714.2mv 1052.2mv 338mv 52.1mv 00221-066 figure 66. ntsc luma video levels 650mv 299.3mv 978mv 0mv peak chroma blank/black level 286mv p-p peak chroma 694.9mv p-p 00221-067 figure 67. ntsc chroma video levels +100 ire 0 ire ?40 ire ref white sync level blank/black level 715.7mv 1052.2mv 336.5mv 51mv 00221-068 figure 68. ntsc rgb video levels
adv7170/adv7171 rev. c | page 46 of 64 pal waveforms 1284.2mv 1047.1mv 350.7mv 50.8mv peak composite ref white sync level blank/black level 696.4mv 00221-069 figure 69. pal composite video levels 1047mv 350.7mv 50.8mv ref white sync level blank/black level 696.4mv 00221-070 figure 70. pal luma video levels 650mv 317.7mv 989.7mv 0mv peak chroma blank/black level 300mv p-p 672mv p-p peak chroma 00221-071 figure 71. pal chroma video levels 1050.2mv 351.8mv 51mv ref white sync level blank/black level 698.4mv 00221-072 figure 72. pal rgb video levels
adv7170/adv7171 rev. c | page 47 of 64 uv waveforms betacam level 0mv +171mv +334mv +505mv 0mv ? 171mv ? 334mv ? 505mv white yellow cyan green magent a red blue black 00221-073 betacam leve l 0mv +82mv +423mv +505mv 0mv ?82mv ?505mv ?423mv white yellow cyan green magent a red blue black 00221-076 figure 76. ntsc 100% color bars, no pedestal v levels figure 73. ntst 100% color bars, no pedestal u levels betacam level 0mv +76mv +391mv +467mv 0mv ? 76mv ? 467mv ? 391mv white yellow cyan green magent a red blue black 00221-077 betacam leve l 0mv +158mv +309mv +467mv 0mv ?158mv ?309mv ?467mv white yellow cyan green magenta red blue black 00221-074 figure 74. ntsc 100% color bars with pedestal u levels figure 77. ntsc 100% color bars with pedestal v levels s mpte level 0mv +118mv +232mv +350mv 0mv ? 118mv ? 232mv ? 350mv white yellow cyan green magent a red blue black 00221-075 s mpte level 0mv +57mv +293mv +350mv 0mv ?57mv ?350mv ?293mv white yellow cyan green magent a red blue black 00221-078 figure 75. pal 100% color bars, u levels figure 78. pal 100% color bars, v levels
adv7170/adv7171 rev. c | page 48 of 64 appendix 7optional output filter if an output filter is required for the cvbs, y, uv, chroma, and rgb outputs of the adv7170/adv7171, the filter shown in figure 79 can be used. plots of the filter characteristics are shown in figure 80 . an output filter is not required if the outputs of the adv7170/adv7171 are connected to most analog monitors or analog tvs. however, if the output signals are applied to a system where sampling is used (for example, digital tvs), then a filter is required to prevent aliasing. 1.8 h 75r 270pf 22pf 330pf filter i/p filter o/p 00221-079 figure 79. output filter 0 80 100k 100m 00221-080 frequency (hz) magnitude (db) 1m 10m 10 20 30 40 50 60 70 figure 80. output filter plot appendix 8optional dac buffering when external buffering of the adv7170/adv7171 dac outputs is needed, the configuration in figure 81 is recom- mended. this configuration shows the dac outputs running at half (18 ma) their full current (36 ma) capability. this allows the adv7170/adv7171 to dissipate less power; the analog current is reduced by 50% with a r set of 300 and a r load of 75 . this mode is recommended for 3.3 v operation, because optimum performance is obtained from the dac outputs at 18 ma with a v aa of 3.3 v. this buffer also adds extra isolation on the video outputs (see the buffer circuit in figure 82 ). when calculating absolute output full-scale current and voltage, use the following equations: load out out riv = ( ) set ref out r kv i = v vconstant, k ref 235.1 2146.4 = = adv7170/adv7171 v ref digital core pixel port 300 r set v aa output buffer dac a output buffer output buffer output buffer dac c dac d dac b cvbs luma chroma cvbs 00221-081 figure 81. output dac buffering configuration v cc + v cc ? output to tv monitor input/ optional filter o/p 5 2 3 1 4 ad8061 00221-082 figure 82. recommended output dac buffer
adv7170/adv7171 rev. c | page 49 of 64 appendix 9recommended register values the adv7170/adv7171 registers can be set depending on the user standard required. the following examples give the various register formats for several video standards. in each case, the output is set to composite o/p with all dacs powered up and with the blank input control disabled. additionally, the burst and color information are enabled on the output and the internal color bar generator is switched off. in the examples shown, the timing mode is set to mode 0 in slave format. tr02 to tr00 of the timing register 0 control the timing modes. for a detailed explanation of each bit in the command registers, please see the section. tr07 should be toggled after setting up a new timing mode. timing register 1 provides additional control over the position and duration of the timing signals. in the examples, this register is programmed in default mode. register programming table 13. pal b/d/g/h/i (f sc = 4.43361875 mhz) address data 00hex mode register 0 05hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss register 0 00hex 17hex cgms_wss register 1 00hex 18hex cgms_wss register 2 00hex 19hex teletext request control register 00hex table 14. pal m (f sc = 3.57561149 mhz) address data 00hex mode register 0 02hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 a3hex 0ahex subcarrier frequency register 1 efhex 0bhex subcarrier frequency register 2 e6hex 0chex subcarrier frequency register 3 21hex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss register 0 00hex 17hex cgms_wss register 1 00hex 18hex cgms_wss register 2 00hex 19hex teletext request control register 00hex
adv7170/adv7171 rev. c | page 50 of 64 table 15. pal n (f sc = 4.43361875 mhz) address data 00hex mode register 0 05hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss register 0 00hex 17hex cgms_wss register 1 00hex 18hex cgms_wss register 2 00hex 19hex teletext request control register 00hex table 16. pal60 (f sc = 4.43361875 mhz) address data 00hex mode register 0 04hex 01hex mode register 1 00hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 00hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 cbhex 0ahex subcarrier frequency register 1 8ahex 0bhex subcarrier frequency register 2 09hex 0chex subcarrier frequency register 3 2ahex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss register 0 00hex 17hex cgms_wss register 1 00hex 18hex cgms_wss register 2 00hex 19hex teletext request control register 00hex table 17. power-up reset values ntsc (f sc = 3.5795454 mhz) address data 00hex mode register 0 00hex 01hex mode register 1 58hex 02hex mode register 2 00hex 03hex mode register 3 00hex 04hex mode register 4 10hex 07hex timing register 0 00hex 08hex timing register 1 00hex 09hex subcarrier frequency register 0 16hex 0ahex subcarrier frequency register 1 7chex 0bhex subcarrier frequency register 2 f0hex 0chex subcarrier frequency register 3 21hex 0dhex subcarrier phase register 00hex 0ehex closed captioning ext register 0 00hex 0fhex closed captioning ext register 1 00hex 10hex closed captioning register 0 00hex 11hex closed captioning register 1 00hex 12hex pedestal control register 0 00hex 13hex pedestal control register 1 00hex 14hex pedestal control register 2 00hex 15hex pedestal control register 3 00hex 16hex cgms_wss register 0 00hex 17hex cgms_wss register 1 00hex 18hex cgms_wss register 2 00hex 19hex teletext request control register 00hex
adv7170/adv7171 rev. c | page 51 of 64 appendix 10output waveforms 0.6 0.4 0.2 0.0 ? 0.2 l608 0.0 10.0 20.0 30.0 40.0 50.0 60.0 microseconds noise reduction: 0.00db apl = 39.1% precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = source slow clamp to 0.00v at 6.72 s frames selected: 1 2 3 4 volts 00221-083 figure 83. 100/0/75/0 pal color bars microseconds apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00v at 6.72 s frames selected: 1 0.5 0.0 l575 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 volts 00221-084 figure 84. 100/0/75/0 pal color bars luminance
adv7170/adv7171 rev. c | page 52 of 64 apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00v at 6.72 s frames selected: 1 0.5 0.0 ?0.5 10.0 30.0 40.0 50.0 60.0 20.0 microseconds l575 volts no bruch signal 00221-085 figure 85. 100/0/75/0 pal color bars chrominance apl = 44.6% precision mode off 525 line ntsc no filtering synchronous sync = a slow clamp to 0.00v at 6.72 s frames selected: 1 2 microseconds 0.5 0.0 ?50.0 50.0 100.0 ire:flt volts f1 l76 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.0 00221-086 figure 86. 100/7.5/75/7.5 ntsc color bars
adv7170/adv7171 rev. c | page 53 of 64 noise reduction: 15.05db apl = 44.7% precision mode off 525 line ntsc no filtering synchronous sync = source slow clamp to 0.00v at 6.72 s frames selected: 1 2 microseconds 10.0 20.0 30.0 40.0 50.0 60.0 0.6 0.4 0.2 0.0 ?0.2 50.0 0.0 ire:flt volts f2 l238 00221-087 figure 87. 100/7.5/75/7.5 ntsc color bars luminance noise reduction: 15.05db apl needs sync = source! precision mode off 525 line ntsc no filtering synchronous sync = b slow clamp to 0.00v at 6.72 s frames selected: 1 2 microseconds 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.4 0.2 0.0 ?0.2 ?0.4 volts 50.0 ?50.0 f1 l76 ire:flt 00221-088 figure 88. 100/7.5/75/7.5 ntsc color bars chrominance
adv7170/adv7171 rev. c | page 54 of 64 apl = 39.6% sound in sync off v u yi yl g r m g cy m g cy g r 75% 100% b b system line l608 angle (deg) 0.0 gain 1.000 0.000db 625 line pal burst from source display +v and ?v 00221-089 figure 89. pal vector plot apl = 45.1% setup 7.5% r?y b?y yi g cy m g cy i r 75% 100% b b q ?q ?i system line l76f1 angle (deg) 0.0 gain 1.000 0.000db 525 line ntsc burst from source 00221-090 figure 90. ntsc vector plot
adv7170/adv7171 rev. c | page 55 of 64 color bar (ntsc) field = 2 line = 28 luminance level (ire) wfm fcc color bar 0.4 0.2 0.2 0.0 0.2 0.1 0.2 0.1 0.0 ? 0.2 ? 0.2 ? 0.3 ? 0.2 ? 0.3 0.0 0.0 . . . . . ? 0.1 ? 0.2 ? 0.2 ? 0.1 ? 0.3 ? 0.2 - - - - - chrominance level (ire) chrominance phase (deg) gray yellow cyan green magenta red blue black average: 32 32 reference 75/7.5/75/7.5 color bar standard 30.0 20.0 10.0 0.0 ?10.0 1.0 0.0 ?1.0 0.0 ? 1.0 ? 2.0 00221-091 figure 91. ntsc color bar measurement dgdp (ntsc) block mode start f2 l64, step = 32, end = 192 differential gain (%) wfm mod 5 step min = ?0.00 max = 0.11 p-p/max = 0.11 0.00 0.08 0.07 0.11 0.07 0.05 0.3 0.2 0.1 0.0 ?0.1 0.20 0.15 0.10 0.05 ? 0.00 ? 0.05 ? 0.10 0.00 0.03 ?0.02 0.14 0.10 0.10 differential phase (deg) min = 0.02 max = 0.14 p-p = 0.16 1st 2nd 3rd 4th 5th 6th 00221-092 figure 92. ntsc differential gain and phase measurement
adv7170/adv7171 rev. c | page 56 of 64 luminance nonlinearity (ntsc) field = 2 line = 21 luminance nonlinearity (%) wfm 5 step p-p = 0.2 99.9 100.0 99.9 99.9 99.8 100.4 100.3 100.2 100.1 100.0 99.9 99.8 99.7 99.6 99.5 99.4 99.3 99.2 99.1 99.0 98.9 98.8 98.7 98.6 1st 2nd 3rd 4th 5th 00221-093 figure 93. ntsc luminance nonlinearity measurement chrominance am pm (ntsc) full field (both fields) bandwidth 100hz to 500khz wfm appropriate ?75.0 am noise ?68.4db rms ?70.0 ?65.0 ?60.0 ?55.0 ?50.0 ?45.0 ?40.0 db rms ?75.0 pm noise ?64.4db rms ?70.0 ?65.0 ?60.0 ?55.0 ?50.0 ?45.0 ?40.0 db rms (0db = 714mv p-p with agc for 100% chrominance level) 00221-094 figure 94. ntsc ampm noise measurement
adv7170/adv7171 rev. c | page 57 of 64 noise spectrum (ntsc) field = 2 line = 64 amplitude (0db = 714mv p-p) bandwidth 100khz to full wfm pedestal noise level = ?80.1db rms ?5.0 ?10.0 ?15.0 ?20.0 ?25.0 ?30.0 ?35.0 ?40.0 ?45.0 ?50.0 ?55.0 ?60.0 ?65.0 ?70.0 ?75.0 ?80.0 ?85.0 ?90.0 ?95.0 ?100.0 1.0 2.0 3.0 4.0 5.0 6.0 (mhz) 00221-095 figure 95. ntsc snr pedestal measurement noise spectrum (ntsc) field = 2 line = 64 amplitude (0db = 714mv p-p) bandwidth 10khz to full (tilt null) wfm ramp signal noise level = ?61.7db rms ?5.0 ?10.0 ?15.0 ?20.0 ?25.0 ?30.0 ?35.0 ?40.0 ?45.0 ?50.0 ?55.0 ?60.0 ?65.0 ?70.0 ?75.0 ?80.0 ?85.0 ?90.0 ?95.0 ? 100.0 1.0 2.0 3.0 4.0 5.0 (mhz) 00221-096 figure 96. ntsc snr ramp measurement
adv7170/adv7171 rev. c | page 58 of 64 parade smpte/ebu pal mv y(a) mv pb(b) mv pr(c) 700 600 500 400 300 200 100 0 ? 100 ? 200 ? 300 250 200 150 100 50 ?50 ?100 ?150 ?200 ?250 250 200 150 100 50 ?50 ?100 ?150 ?200 ?250 0 00221-097 0 figure 97. pal yuv parade plot lightning colorbars: 75% smpte/ebu (50hz) pk-white (100%) 700.0mv setup 0.0% color p-p 525.0mv average 32 32 l183 y i ? 274.82 0.93% g ?173.24 0.19% r ?88.36 0.19% cy 88.31 0.28% m 174.35 ?0.65% b 260.51 ?0.14% y i 462.80 ? 0.50% g 307.54 ? 0.21% r 156.63 ? 0.22% b?y w yi g r b g cy r?y w yi m r cy ?262.17 ?0.13% g ?218.70 ?0.51% b ?42.54 0.69% yi 41.32 ?0.76% m 212.28 ?3.43% r 252.74 ?3.72% cy 864.78 ?0.88% m 216.12 ?0.33% b 61.00 1.92% cy m b color pk-pk: b?y 532.33mv 1.40% pk-white: 700.4mv (100%) setup ?0.01% r?y 514.90mv ?1.92% delay: b?y ?6ns r?y ?6ns 00221-098 figure 98. pal yuv lighting plot
adv7170/adv7171 rev. c | page 59 of 64 component noise line = 202 amplitude (0db = 700mv p-p) bandwidth 10khz to 5.0mhz noise db rms ?5.0 ?10.0 ?15.0 ?20.0 ?25.0 ?30.0 ?35.0 ?40.0 ?45.0 ?50.0 ?55.0 ?60.0 ?65.0 ?70.0 ?75.0 ?80.0 ?85.0 ?90.0 ?95.0 ? 100.0 1.0 2.0 3.0 4.0 5.0 (mhz) 6.0 0.0 y 82.1 pb 82.3 pr 83.3 00221-099 figure 99. pal yuv snr plot component multiburst line = 202 amplitude (0db = 100% of 688.1mv 683.4mv 668.9mv) 0.04 ?0.02 ?0.05 ?0.68 ?2.58 ?8.05 (db) 0.49 0.99 2.00 3.99 4.79 5.79 0.49 0.99 1.99 2.39 2.89 0.49 0.99 1.99 2.39 2.89 0.0 ?5.0 ?10.0 y 0.0 ?5.0 ?10.0 pb 0.0 ?5.0 ?10.0 pr (mhz) 0.21 0.23 ?0.78 ?2.59 ?7.15 0.25 0.25 ?0.77 ?2.59 ?7.13 00221-100 figure 100. pal yuv multiburst response
adv7170/adv7171 rev. c | page 60 of 64 r m g yi bk b g cy component vector smpte/ebu, 75% 00221-101 figure 101. pal yuv vector plot mv green (a) mv blue (b) mv red (c) 700 600 500 400 300 200 100 0 ? 100 ? 200 ? 300 700 600 500 400 300 200 100 0 700 600 500 400 300 200 100 0 ?100 ?200 ?300 ?100 ?200 ?300 00221-102 figure 102. pal rgb waveforms
adv7170/adv7171 rev. c | page 61 of 64 outline dimensions compliant to jedec standards mo-112-aa-1 041807-a 14.15 13.90 sq 13.65 0.45 0.30 2.45 max 1.03 0.88 0.73 top view (pins down) 12 44 1 22 23 34 33 11 0.25 min 2.20 2.00 1.80 7 0 view a rotated 90 ccw 0.23 0.11 10.20 10.00 sq 9.80 0.80 bsc lead pitch lead width 0.10 coplanarity v i e w a s e a t i n g p l a n e 1 . 9 5 r e f pin 1 figure 103. 44-lead thin plas tic quad flat package [mqfp] (s-44-2) dimensions shown in millimeters compliant to jedec standards ms-026acb 1 33 34 44 11 12 23 22 0.45 0.37 0.30 0.80 bsc lead pitch 10.00 bsc sq 12.00 bsc sq 1.20 max 0.75 0.60 0.45 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity seating plane 0 min 7 3.5 0 0.15 0.05 view a rotated 90 ccw view a pin 1 top view (pins down) figure 104. 44-lead thin plastic quad flat package [tqfp] (su-44) dimensions shown in millimeters
adv7170/adv7171 rev. c | page 62 of 64 compliant to jedec standards ms-022-ab-1 041807-a 13.45 13.20 sq 12.95 0.45 0.29 2.45 max 1.03 0.88 0.73 top view (pins down) 12 44 1 22 23 34 33 11 0.25 0.10 2.20 2.00 1.80 7 0 view a rotated 90 ccw 0.23 0.11 10.20 10.00 sq 9.80 0.80 bsc lead pitch lead width 0.10 coplanarity v i e w a s e a t i n g p l a n e 1 . 6 0 r e f pin 1 figure 105. 44-lead metric quad flat package [mqfp] (s-44-1) dimensions shown in millimeters ordering guide model temperature range package descriptions package options adv7170ksz 1 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-2 adv7170ksz-reel 1 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-2 adv7170ksuz 1 ?40c to +85c 44-lead thin plastic quad flat package [tqfp] su-44 adv7170ksuz-reel 1 ?40c to +85c 44-lead thin plastic quad flat package [tqfp] su-44 adv7171ksz 1 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-2 adv7171ksz-reel 1 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-2 adv7171ksuz 1 ?40c to +85c 44-lead thin plastic quad flat package [tqfp] su-44 ADV7171KSUZ-REEL 1 ?40c to +85c 44-lead thin plastic quad flat package [tqfp] su-44 adv7171wbsz-reel 1 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-1 eval-adv7170ebm evaluation board eval-adv7171ebm evaluation board 1 z = rohs compliant part.
adv7170/adv7171 rev. c | page 63 of 64 notes
adv7170/adv7171 rev. c | page 64 of 64 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2002C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. printed in the u.s.a. d00221-0-3/09(c)

▲Up To Search▲

Price & Availability of ADV7171KSUZ-REEL

	To Download ADV7171KSUZ-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .